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timer-davinci.h��0000644��00000002437�14722070607�0007463 0��ustar�00��/* SPDX-License-Identifier: GPL-2.0-only / / * TI DaVinci clocksource driver * * Copyright (C) 2019 Texas Instruments * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com> / #ifndef __TIMER_DAVINCI_H__ #define __TIMER_DAVINCI_H__ #include <linux/clk.h> #include <linux/ioport.h> enum { DAVINCI_TIMER_CLOCKEVENT_IRQ, DAVINCI_TIMER_CLOCKSOURCE_IRQ, DAVINCI_TIMER_NUM_IRQS, }; /* * struct davinci_timer_cfg - davinci clocksource driver configuration struct * @reg: register range resource * @irq: clockevent and clocksource interrupt resources * @cmp_off: if set - it specifies the compare register used for clockevent * * Note: if the compare register is specified, the driver will use the bottom * clock half for both clocksource and clockevent and the compare register * to generate event irqs. The user must supply the correct compare register * interrupt number. * * This is only used by da830 the DSP of which uses the top half. The timer * driver still configures the top half to run in free-run mode. / struct davinci_timer_cfg { struct resource reg; struct resource irq[DAVINCI_TIMER_NUM_IRQS]; unsigned int cmp_off; }; int __init davinci_timer_register(struct clk clk, const struct davinci_timer_cfg data); #endif / __TIMER_DAVINCI_H__ / ��pxa.h��0000644��00000000426�14722070607�0005514 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0-only / / * PXA clocksource, clockevents, and OST interrupt handlers. * * Copyright (C) 2014 Robert Jarzmik / #ifndef _CLOCKSOURCE_PXA_H #define _CLOCKSOURCE_PXA_H extern void pxa_timer_nodt_init(int irq, void __iomem base); #endif ��samsung_pwm.h��0000644��00000001423�14722070607�0007262 0��ustar�00��/* SPDX-License-Identifier: GPL-2.0-only / / * Copyright (C) 2013 Samsung Electronics Co., Ltd. / #ifndef __CLOCKSOURCE_SAMSUNG_PWM_H #define __CLOCKSOURCE_SAMSUNG_PWM_H #include <linux/spinlock.h> #define SAMSUNG_PWM_NUM 5 / * Following declaration must be in an ifdef due to this symbol being static * in pwm-samsung driver if the clocksource driver is not compiled in and the * spinlock is not shared between both drivers. / #ifdef CONFIG_CLKSRC_SAMSUNG_PWM extern spinlock_t samsung_pwm_lock; #endif struct samsung_pwm_variant { u8 bits; u8 div_base; u8 tclk_mask; u8 output_mask; bool has_tint_cstat; }; void samsung_pwm_clocksource_init(void __iomem base, unsigned int irqs, struct samsung_pwm_variant variant); #endif /* __CLOCKSOURCE_SAMSUNG_PWM_H / ��timer-sp804.h��0000644��00000001520�14722070607�0006714 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0 / #ifndef __CLKSOURCE_TIMER_SP804_H #define __CLKSOURCE_TIMER_SP804_H struct clk; int __sp804_clocksource_and_sched_clock_init(void __iomem , const char , struct clk , int); int __sp804_clockevents_init(void __iomem , unsigned int, struct clk , const char ); void sp804_timer_disable(void __iomem ); static inline void sp804_clocksource_init(void __iomem base, const char name) { __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); } static inline void sp804_clocksource_and_sched_clock_init(void __iomem base, const char name) { __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); } static inline void sp804_clockevents_init(void __iomem base, unsigned int irq, const char name) { __sp804_clockevents_init(base, irq, NULL, name); } #endif ��arm_arch_timer.h��0000644��00000004701�14722070607�0007700 0��ustar�00��/* SPDX-License-Identifier: GPL-2.0-only / / * Copyright (C) 2012 ARM Ltd. / #ifndef __CLKSOURCE_ARM_ARCH_TIMER_H #define __CLKSOURCE_ARM_ARCH_TIMER_H #include <linux/bitops.h> #include <linux/timecounter.h> #include <linux/types.h> #define ARCH_TIMER_TYPE_CP15 BIT(0) #define ARCH_TIMER_TYPE_MEM BIT(1) #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) #define CNTHCTL_EL1PCTEN (1 << 0) #define CNTHCTL_EL1PCEN (1 << 1) #define CNTHCTL_EVNTEN (1 << 2) #define CNTHCTL_EVNTDIR (1 << 3) #define CNTHCTL_EVNTI (0xF << 4) enum arch_timer_reg { ARCH_TIMER_REG_CTRL, ARCH_TIMER_REG_TVAL, }; enum arch_timer_ppi_nr { ARCH_TIMER_PHYS_SECURE_PPI, ARCH_TIMER_PHYS_NONSECURE_PPI, ARCH_TIMER_VIRT_PPI, ARCH_TIMER_HYP_PPI, ARCH_TIMER_MAX_TIMER_PPI }; enum arch_timer_spi_nr { ARCH_TIMER_PHYS_SPI, ARCH_TIMER_VIRT_SPI, ARCH_TIMER_MAX_TIMER_SPI }; #define ARCH_TIMER_PHYS_ACCESS 0 #define ARCH_TIMER_VIRT_ACCESS 1 #define ARCH_TIMER_MEM_PHYS_ACCESS 2 #define ARCH_TIMER_MEM_VIRT_ACCESS 3 #define ARCH_TIMER_MEM_MAX_FRAMES 8 #define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) / physical counter / #define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) / virtual counter / #define ARCH_TIMER_VIRT_EVT_EN (1 << 2) #define ARCH_TIMER_EVT_TRIGGER_SHIFT (4) #define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT) #define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) / virtual timer registers / #define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) / physical timer registers / #define ARCH_TIMER_EVT_STREAM_PERIOD_US 100 #define ARCH_TIMER_EVT_STREAM_FREQ \ (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US) struct arch_timer_kvm_info { struct timecounter timecounter; int virtual_irq; int physical_irq; }; struct arch_timer_mem_frame { bool valid; phys_addr_t cntbase; size_t size; int phys_irq; int virt_irq; }; struct arch_timer_mem { phys_addr_t cntctlbase; size_t size; struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES]; }; #ifdef CONFIG_ARM_ARCH_TIMER extern u32 arch_timer_get_rate(void); extern u64 (arch_timer_read_counter)(void); extern struct arch_timer_kvm_info arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); #else static inline u32 arch_timer_get_rate(void) { return 0; } static inline u64 arch_timer_read_counter(void) { return 0; } static inline bool arch_timer_evtstrm_available(void) { return false; } #endif #endif ��hyperv_timer.h��0000644��00000005535�14722070607�0007447 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0 / / * Definitions for the clocksource provided by the Hyper-V * hypervisor to guest VMs, as described in the Hyper-V Top * Level Functional Spec (TLFS). * * Copyright (C) 2019, Microsoft, Inc. * * Author: Michael Kelley <mikelley@microsoft.com> / #ifndef __CLKSOURCE_HYPERV_TIMER_H #define __CLKSOURCE_HYPERV_TIMER_H #include <linux/clocksource.h> #include <linux/math64.h> #include <asm/mshyperv.h> #define HV_MAX_MAX_DELTA_TICKS 0xffffffff #define HV_MIN_DELTA_TICKS 1 / Routines called by the VMbus driver / extern int hv_stimer_alloc(int sint); extern void hv_stimer_free(void); extern void hv_stimer_init(unsigned int cpu); extern void hv_stimer_cleanup(unsigned int cpu); extern void hv_stimer_global_cleanup(void); extern void hv_stimer0_isr(void); #ifdef CONFIG_HYPERV_TIMER extern struct clocksource hyperv_cs; extern void hv_init_clocksource(void); extern struct ms_hyperv_tsc_page hv_get_tsc_page(void); static inline notrace u64 hv_read_tsc_page_tsc(const struct ms_hyperv_tsc_page tsc_pg, u64 cur_tsc) { u64 scale, offset; u32 sequence; / * The protocol for reading Hyper-V TSC page is specified in Hypervisor * Top-Level Functional Specification ver. 3.0 and above. To get the * reference time we must do the following: * - READ ReferenceTscSequence * A special '0' value indicates the time source is unreliable and we * need to use something else. The currently published specification * versions (up to 4.0b) contain a mistake and wrongly claim '-1' * instead of '0' as the special value, see commit c35b82ef0294. * - ReferenceTime = * ((RDTSC() * ReferenceTscScale) >> 64) + ReferenceTscOffset * - READ ReferenceTscSequence again. In case its value has changed * since our first reading we need to discard ReferenceTime and repeat * the whole sequence as the hypervisor was updating the page in * between. / do { sequence = READ_ONCE(tsc_pg->tsc_sequence); if (!sequence) return U64_MAX; / * Make sure we read sequence before we read other values from * TSC page. / smp_rmb(); scale = READ_ONCE(tsc_pg->tsc_scale); offset = READ_ONCE(tsc_pg->tsc_offset); cur_tsc = hv_get_raw_timer(); /* * Make sure we read sequence after we read all other values * from TSC page. / smp_rmb(); } while (READ_ONCE(tsc_pg->tsc_sequence) != sequence); return mul_u64_u64_shr(cur_tsc, scale, 64) + offset; } static inline notrace u64 hv_read_tsc_page(const struct ms_hyperv_tsc_page tsc_pg) { u64 cur_tsc; return hv_read_tsc_page_tsc(tsc_pg, &cur_tsc); } #else / CONFIG_HYPERV_TIMER / static inline struct ms_hyperv_tsc_page hv_get_tsc_page(void) { return NULL; } static inline u64 hv_read_tsc_page_tsc(const struct ms_hyperv_tsc_page tsc_pg, u64 cur_tsc) { return U64_MAX; } #endif /* CONFIG_HYPERV_TIMER / #endif ��timer-ti-dm.h��0000644��00000030510�14722070607�0007051 0��ustar�00��/ * OMAP Dual-Mode Timers * * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ * Tarun Kanti DebBarma <tarun.kanti@ti.com> * Thara Gopinath <thara@ti.com> * * Platform device conversion and hwmod support. * * Copyright (C) 2005 Nokia Corporation * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> * PWM and clock framwork support by Timo Teras. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. / #include <linux/delay.h> #include <linux/io.h> #include <linux/platform_device.h> #ifndef __CLOCKSOURCE_DMTIMER_H #define __CLOCKSOURCE_DMTIMER_H / clock sources / #define OMAP_TIMER_SRC_SYS_CLK 0x00 #define OMAP_TIMER_SRC_32_KHZ 0x01 #define OMAP_TIMER_SRC_EXT_CLK 0x02 / timer interrupt enable bits / #define OMAP_TIMER_INT_CAPTURE (1 << 2) #define OMAP_TIMER_INT_OVERFLOW (1 << 1) #define OMAP_TIMER_INT_MATCH (1 << 0) / trigger types / #define OMAP_TIMER_TRIGGER_NONE 0x00 #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 / posted mode types / #define OMAP_TIMER_NONPOSTED 0x00 #define OMAP_TIMER_POSTED 0x01 / timer capabilities used in hwmod database / #define OMAP_TIMER_SECURE 0x80000000 #define OMAP_TIMER_ALWON 0x40000000 #define OMAP_TIMER_HAS_PWM 0x20000000 #define OMAP_TIMER_NEEDS_RESET 0x10000000 #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 / * timer errata flags * * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This * errata prevents us from using posted mode on these devices, unless the * timer counter register is never read. For more details please refer to * the OMAP3/4/5 errata documents. / #define OMAP_TIMER_ERRATA_I103_I767 0x80000000 struct timer_regs { u32 tidr; u32 tier; u32 twer; u32 tclr; u32 tcrr; u32 tldr; u32 ttrg; u32 twps; u32 tmar; u32 tcar1; u32 tsicr; u32 tcar2; u32 tpir; u32 tnir; u32 tcvr; u32 tocr; u32 towr; }; struct omap_dm_timer { int id; int irq; struct clk fclk; void __iomem io_base; void __iomem irq_stat; /* TISR/IRQSTATUS interrupt status / void __iomem irq_ena; /* irq enable / void __iomem irq_dis; /* irq disable, only on v2 ip / void __iomem pend; /* write pending / void __iomem func_base; /* function register base / unsigned long rate; unsigned reserved:1; unsigned posted:1; struct timer_regs context; int (get_context_loss_count)(struct device ); int ctx_loss_count; int revision; u32 capability; u32 errata; struct platform_device pdev; struct list_head node; }; int omap_dm_timer_reserve_systimer(int id); struct omap_dm_timer omap_dm_timer_request_by_cap(u32 cap); int omap_dm_timer_get_irq(struct omap_dm_timer timer); u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); int omap_dm_timer_trigger(struct omap_dm_timer timer); int omap_dm_timers_active(void); / * Do not use the defines below, they are not needed. They should be only * used by dmtimer.c and sys_timer related code. / / * The interrupt registers are different between v1 and v2 ip. * These registers are offsets from timer->iobase. / #define OMAP_TIMER_ID_OFFSET 0x00 #define OMAP_TIMER_OCP_CFG_OFFSET 0x10 #define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14 #define OMAP_TIMER_V1_STAT_OFFSET 0x18 #define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c #define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24 #define OMAP_TIMER_V2_IRQSTATUS 0x28 #define OMAP_TIMER_V2_IRQENABLE_SET 0x2c #define OMAP_TIMER_V2_IRQENABLE_CLR 0x30 / * The functional registers have a different base on v1 and v2 ip. * These registers are offsets from timer->func_base. The func_base * is samae as io_base for v1 and io_base + 0x14 for v2 ip. * / #define OMAP_TIMER_V2_FUNC_OFFSET 0x14 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 #define _OMAP_TIMER_CTRL_OFFSET 0x24 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14) #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) #define OMAP_TIMER_CTRL_PT (1 << 12) #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) #define OMAP_TIMER_CTRL_SCPWM (1 << 7) #define OMAP_TIMER_CTRL_CE (1 << 6) / compare enable / #define OMAP_TIMER_CTRL_PRE (1 << 5) / prescaler enable / #define OMAP_TIMER_CTRL_PTV_SHIFT 2 / prescaler value shift / #define OMAP_TIMER_CTRL_POSTED (1 << 2) #define OMAP_TIMER_CTRL_AR (1 << 1) / auto-reload enable / #define OMAP_TIMER_CTRL_ST (1 << 0) / start timer / #define _OMAP_TIMER_COUNTER_OFFSET 0x28 #define _OMAP_TIMER_LOAD_OFFSET 0x2c #define _OMAP_TIMER_TRIGGER_OFFSET 0x30 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34 #define WP_NONE 0 / no write pending bit / #define WP_TCLR (1 << 0) #define WP_TCRR (1 << 1) #define WP_TLDR (1 << 2) #define WP_TTGR (1 << 3) #define WP_TMAR (1 << 4) #define WP_TPIR (1 << 5) #define WP_TNIR (1 << 6) #define WP_TCVR (1 << 7) #define WP_TOCR (1 << 8) #define WP_TOWR (1 << 9) #define _OMAP_TIMER_MATCH_OFFSET 0x38 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 / TCAR2, 34xx only / #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 / TPIR, 34xx only / #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c / TNIR, 34xx only / #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 / TCVR, 34xx only / #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 / TOCR, 34xx only / #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 / TOWR, 34xx only / / register offsets with the write pending bit encoded / #define WPSHIFT 16 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ \| (WP_NONE << WPSHIFT)) #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ \| (WP_TCLR << WPSHIFT)) #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ \| (WP_TCRR << WPSHIFT)) #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ \| (WP_TLDR << WPSHIFT)) #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ \| (WP_TTGR << WPSHIFT)) #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ \| (WP_NONE << WPSHIFT)) #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ \| (WP_TMAR << WPSHIFT)) #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ \| (WP_NONE << WPSHIFT)) #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ \| (WP_NONE << WPSHIFT)) #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ \| (WP_NONE << WPSHIFT)) #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ \| (WP_TPIR << WPSHIFT)) #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ \| (WP_TNIR << WPSHIFT)) #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ \| (WP_TCVR << WPSHIFT)) #define OMAP_TIMER_TICK_INT_MASK_SET_REG \ (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET \| (WP_TOCR << WPSHIFT)) #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET \| (WP_TOWR << WPSHIFT)) / * The below are inlined to optimize code size for system timers. Other code * should not need these at all, see * include/linux/platform_data/pwm_omap_dmtimer.h / #if defined(CONFIG_ARCH_OMAP1) \|\| defined(CONFIG_ARCH_OMAP2PLUS) static inline u32 __omap_dm_timer_read(struct omap_dm_timer timer, u32 reg, int posted) { if (posted) while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); return readl_relaxed(timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_write(struct omap_dm_timer timer, u32 reg, u32 val, int posted) { if (posted) while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); writel_relaxed(val, timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_init_regs(struct omap_dm_timer timer) { u32 tidr; /* Assume v1 ip if bits [31:16] are zero / tidr = readl_relaxed(timer->io_base); if (!(tidr >> 16)) { timer->revision = 1; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; timer->func_base = timer->io_base; } else { timer->revision = 2; timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET + OMAP_TIMER_V2_FUNC_OFFSET; timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; } } / * __omap_dm_timer_enable_posted - enables write posted mode * @timer: pointer to timer instance handle * * Enables the write posted mode for the timer. When posted mode is enabled * writes to certain timer registers are immediately acknowledged by the * internal bus and hence prevents stalling the CPU waiting for the write to * complete. Enabling this feature can improve performance for writing to the * timer registers. / static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer timer) { if (timer->posted) return; if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { timer->posted = OMAP_TIMER_NONPOSTED; __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0); return; } __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED, 0); timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; timer->posted = OMAP_TIMER_POSTED; } /** * __omap_dm_timer_override_errata - override errata flags for a timer * @timer: pointer to timer handle * @errata: errata flags to be ignored * * For a given timer, override a timer errata by clearing the flags * specified by the errata argument. A specific erratum should only be * overridden for a timer if the timer is used in such a way the erratum * has no impact. / static inline void __omap_dm_timer_override_errata(struct omap_dm_timer timer, u32 errata) { timer->errata &= ~errata; } static inline void __omap_dm_timer_stop(struct omap_dm_timer timer, int posted, unsigned long rate) { u32 l; l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); if (l & OMAP_TIMER_CTRL_ST) { l &= ~0x1; __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted); #ifdef CONFIG_ARCH_OMAP2PLUS / Readback to make sure write has completed / __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); / * Wait for functional clock period x 3.5 to make sure that * timer is stopped / udelay(3500000 / rate + 1); #endif } / Ack possibly pending interrupt / writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); } static inline void __omap_dm_timer_load_start(struct omap_dm_timer timer, u32 ctrl, unsigned int load, int posted) { __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted); __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted); } static inline void __omap_dm_timer_int_enable(struct omap_dm_timer timer, unsigned int value) { writel_relaxed(value, timer->irq_ena); __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); } static inline unsigned int __omap_dm_timer_read_counter(struct omap_dm_timer timer, int posted) { return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted); } static inline void __omap_dm_timer_write_status(struct omap_dm_timer timer, unsigned int value) { writel_relaxed(value, timer->irq_stat); } #endif / CONFIG_ARCH_OMAP1 \|\| CONFIG_ARCH_OMAP2PLUS / #endif / __CLOCKSOURCE_DMTIMER_H */ ��Kconfig��0000644��00000044500�14722071066�0006057 0��ustar�00��# SPDX-License-Identifier: GPL-2.0-only menu "Clock Source drivers" depends on GENERIC_CLOCKEVENTS config TIMER_OF bool select TIMER_PROBE config TIMER_ACPI bool select TIMER_PROBE config TIMER_PROBE bool config CLKSRC_I8253 bool config CLKEVT_I8253 bool config I8253_LOCK bool config OMAP_DM_TIMER bool select TIMER_OF config CLKBLD_I8253 def_bool y if CLKSRC_I8253 \|\| CLKEVT_I8253 \|\| I8253_LOCK config CLKSRC_MMIO bool config BCM2835_TIMER bool "BCM2835 timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables the support for the BCM2835 timer driver. config BCM_KONA_TIMER bool "BCM mobile timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables the support for the BCM Kona mobile timer driver. config DAVINCI_TIMER bool "Texas Instruments DaVinci timer driver" if COMPILE_TEST help Enables the support for the TI DaVinci timer driver. config DIGICOLOR_TIMER bool "Digicolor timer driver" if COMPILE_TEST select CLKSRC_MMIO depends on HAS_IOMEM help Enables the support for the digicolor timer driver. config DW_APB_TIMER bool "DW APB timer driver" if COMPILE_TEST help Enables the support for the dw_apb timer. config DW_APB_TIMER_OF bool select DW_APB_TIMER select TIMER_OF config FTTMR010_TIMER bool "Faraday Technology timer driver" if COMPILE_TEST depends on HAS_IOMEM select CLKSRC_MMIO select TIMER_OF select MFD_SYSCON help Enables support for the Faraday Technology timer block FTTMR010. config IXP4XX_TIMER bool "Intel XScale IXP4xx timer driver" if COMPILE_TEST depends on HAS_IOMEM select CLKSRC_MMIO select TIMER_OF if OF help Enables support for the Intel XScale IXP4xx SoC timer. config ROCKCHIP_TIMER bool "Rockchip timer driver" if COMPILE_TEST depends on ARM \|\| ARM64 select TIMER_OF select CLKSRC_MMIO help Enables the support for the rockchip timer driver. config ARMADA_370_XP_TIMER bool "Armada 370 and XP timer driver" if COMPILE_TEST depends on ARM select TIMER_OF select CLKSRC_MMIO help Enables the support for the Armada 370 and XP timer driver. config MESON6_TIMER bool "Meson6 timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables the support for the Meson6 timer driver. config ORION_TIMER bool "Orion timer driver" if COMPILE_TEST depends on ARM select TIMER_OF select CLKSRC_MMIO help Enables the support for the Orion timer driver config OWL_TIMER bool "Owl timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables the support for the Actions Semi Owl timer driver. config RDA_TIMER bool "RDA timer driver" if COMPILE_TEST depends on GENERIC_CLOCKEVENTS select CLKSRC_MMIO select TIMER_OF help Enables the support for the RDA Micro timer driver. config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on HAS_IOMEM select CLKSRC_MMIO select TIMER_OF help Enables support for the Sun4i timer. config SUN5I_HSTIMER bool "Sun5i timer driver" if COMPILE_TEST select CLKSRC_MMIO depends on COMMON_CLK help Enables support the Sun5i timer. config TEGRA_TIMER bool "Tegra timer driver" if COMPILE_TEST select CLKSRC_MMIO select TIMER_OF depends on ARCH_TEGRA \|\| COMPILE_TEST help Enables support for the Tegra driver. config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST depends on HAS_IOMEM help Enables support for the VT8500 driver. config NPCM7XX_TIMER bool "NPCM7xx timer driver" if COMPILE_TEST depends on HAS_IOMEM select TIMER_OF select CLKSRC_MMIO help Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture, While TIMER0 serves as clockevent and TIMER1 serves as clocksource. config CADENCE_TTC_TIMER bool "Cadence TTC timer driver" if COMPILE_TEST depends on COMMON_CLK help Enables support for the cadence ttc driver. config ASM9260_TIMER bool "ASM9260 timer driver" if COMPILE_TEST select CLKSRC_MMIO select TIMER_OF help Enables support for the ASM9260 timer. config CLKSRC_NOMADIK_MTU bool "Nomakdik clocksource driver" if COMPILE_TEST depends on ARM select CLKSRC_MMIO help Support for Multi Timer Unit. MTU provides access to multiple interrupt generating programmable 32-bit free running decrementing counters. config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" if COMPILE_TEST depends on HAS_IOMEM help Use the always on PRCMU Timer as clocksource config CLPS711X_TIMER bool "Cirrus logic timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables support for the Cirrus Logic PS711 timer. config ATLAS7_TIMER bool "Atlas7 timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables support for the Atlas7 timer. config MXS_TIMER bool "Mxs timer driver" if COMPILE_TEST select CLKSRC_MMIO select STMP_DEVICE help Enables support for the Mxs timer. config PRIMA2_TIMER bool "Prima2 timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables support for the Prima2 timer. config U300_TIMER bool "U300 timer driver" if COMPILE_TEST depends on ARM select CLKSRC_MMIO help Enables support for the U300 timer. config NSPIRE_TIMER bool "NSpire timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables support for the Nspire timer. config KEYSTONE_TIMER bool "Keystone timer driver" if COMPILE_TEST depends on ARM \|\| ARM64 select CLKSRC_MMIO help Enables support for the Keystone timer. config INTEGRATOR_AP_TIMER bool "Integrator-ap timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables support for the Integrator-ap timer. config CLKSRC_EFM32 bool "Clocksource for Energy Micro's EFM32 SoCs" if !ARCH_EFM32 depends on OF && ARM && (ARCH_EFM32 \|\| COMPILE_TEST) select CLKSRC_MMIO default ARCH_EFM32 help Support to use the timers of EFM32 SoCs as clock source and clock event device. config CLKSRC_LPC32XX bool "Clocksource for LPC32XX" if COMPILE_TEST depends on HAS_IOMEM depends on ARM select CLKSRC_MMIO select TIMER_OF help Support for the LPC32XX clocksource. config CLKSRC_PISTACHIO bool "Clocksource for Pistachio SoC" if COMPILE_TEST depends on HAS_IOMEM select TIMER_OF help Enables the clocksource for the Pistachio SoC. config CLKSRC_TI_32K bool "Texas Instruments 32.768 Hz Clocksource" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK select TIMER_OF if OF help This option enables support for Texas Instruments 32.768 Hz clocksource available on many OMAP-like platforms. config CLKSRC_NPS bool "NPS400 clocksource driver" if COMPILE_TEST depends on !PHYS_ADDR_T_64BIT select CLKSRC_MMIO select TIMER_OF if OF help NPS400 clocksource support. Got 64 bit counter with update rate up to 1000MHz. This counter is accessed via couple of 32 bit memory mapped registers. config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 \|\| COMPILE_TEST) select CLKSRC_MMIO select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK select CLKSRC_MMIO select TIMER_OF config ARC_TIMERS bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK select TIMER_OF help These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores (ARC700 as well as ARC HS38). TIMER0 serves as clockevent while TIMER1 provides clocksource config ARC_TIMERS_64BIT bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST depends on ARC_TIMERS select TIMER_OF help This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP) RTC is implemented inside the core, while GFRC sits outside the core in ARConnect IP block. Driver automatically picks one of them for clocksource as appropriate. config ARM_ARCH_TIMER bool select TIMER_OF if OF select TIMER_ACPI if ACPI config ARM_ARCH_TIMER_EVTSTREAM bool "Enable ARM architected timer event stream generation by default" default y if ARM_ARCH_TIMER depends on ARM_ARCH_TIMER help This option enables support by default for event stream generation based on the ARM architected timer. It is used for waking up CPUs executing the wfe instruction at a frequency represented as a power-of-2 divisor of the clock rate. The behaviour can also be overridden on the command line using the clocksource.arm_arch_timer.evtstream parameter. The main use of the event stream is wfe-based timeouts of userspace locking implementations. It might also be useful for imposing timeout on wfe to safeguard against any programming errors in case an expected event is not generated. This must be disabled for hardware validation purposes to detect any hardware anomalies of missing events. config ARM_ARCH_TIMER_OOL_WORKAROUND bool config FSL_ERRATUM_A008585 bool "Workaround for Freescale/NXP Erratum A-008585" default y depends on ARM_ARCH_TIMER && ARM64 select ARM_ARCH_TIMER_OOL_WORKAROUND help This option enables a workaround for Freescale/NXP Erratum A-008585 ("ARM generic timer may contain an erroneous value"). The workaround will only be active if the fsl,erratum-a008585 property is found in the timer node. config HISILICON_ERRATUM_161010101 bool "Workaround for Hisilicon Erratum 161010101" default y select ARM_ARCH_TIMER_OOL_WORKAROUND depends on ARM_ARCH_TIMER && ARM64 help This option enables a workaround for Hisilicon Erratum 161010101. The workaround will be active if the hisilicon,erratum-161010101 property is found in the timer node. config ARM64_ERRATUM_858921 bool "Workaround for Cortex-A73 erratum 858921" default y select ARM_ARCH_TIMER_OOL_WORKAROUND depends on ARM_ARCH_TIMER && ARM64 help This option enables a workaround applicable to Cortex-A73 (all versions), whose counter may return incorrect values. The workaround will be dynamically enabled when an affected core is detected. config SUN50I_ERRATUM_UNKNOWN1 bool "Workaround for Allwinner A64 erratum UNKNOWN1" default y depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI select ARM_ARCH_TIMER_OOL_WORKAROUND help This option enables a workaround for instability in the timer on the Allwinner A64 SoC. The workaround will only be active if the allwinner,erratum-unknown1 property is found in the timer node. config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select TIMER_OF if OF depends on ARM help This options enables support for the ARM global timer unit config ARM_TIMER_SP804 bool "Support for Dual Timer SP804 module" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP select CLKSRC_MMIO select TIMER_OF if OF config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK bool depends on ARM_GLOBAL_TIMER default y help Use ARM global timer clock source as sched_clock config ARMV7M_SYSTICK bool "Support for the ARMv7M system time" if COMPILE_TEST select TIMER_OF if OF select CLKSRC_MMIO help This options enables support for the ARMv7M system timer unit config ATMEL_PIT bool "Atmel PIT support" if COMPILE_TEST depends on HAS_IOMEM select TIMER_OF if OF help Support for the Periodic Interval Timer found on Atmel SoCs. config ATMEL_ST bool "Atmel ST timer support" if COMPILE_TEST depends on HAS_IOMEM select TIMER_OF select MFD_SYSCON help Support for the Atmel ST timer. config ATMEL_TCB_CLKSRC bool "Atmel TC Block timer driver" if COMPILE_TEST depends on ARM && HAS_IOMEM select TIMER_OF if OF help Support for Timer Counter Blocks on Atmel SoCs. config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM \|\| ARM64 help Support for Multi Core Timer controller on Exynos SoCs. config CLKSRC_SAMSUNG_PWM bool "PWM timer driver for Samsung S3C, S5P" if COMPILE_TEST depends on HAS_IOMEM help This is a new clocksource driver for the PWM timer found in Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver for all devicetree enabled platforms. This driver will be needed only on systems that do not have the Exynos MCT available. config FSL_FTM_TIMER bool "Freescale FlexTimer Module driver" if COMPILE_TEST depends on HAS_IOMEM select CLKSRC_MMIO help Support for Freescale FlexTimer Module (FTM) timer. config VF_PIT_TIMER bool select CLKSRC_MMIO help Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. config OXNAS_RPS_TIMER bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST select TIMER_OF select CLKSRC_MMIO help This enables support for the Oxford Semiconductor OXNAS RPS timers. config SYS_SUPPORTS_SH_CMT bool config MTK_TIMER bool "Mediatek timer driver" if COMPILE_TEST depends on HAS_IOMEM select TIMER_OF select CLKSRC_MMIO help Support for Mediatek timer driver. config SPRD_TIMER bool "Spreadtrum timer driver" if EXPERT depends on HAS_IOMEM depends on (ARCH_SPRD \|\| COMPILE_TEST) default ARCH_SPRD select TIMER_OF help Enables support for the Spreadtrum timer driver. config SYS_SUPPORTS_SH_MTU2 bool config SYS_SUPPORTS_SH_TMU bool config SYS_SUPPORTS_EM_STI bool config CLKSRC_JCORE_PIT bool "J-Core PIT timer driver" if COMPILE_TEST depends on OF depends on HAS_IOMEM select CLKSRC_MMIO help This enables build of clocksource and clockevent driver for the integrated PIT in the J-Core synthesizable, open source SoC. config SH_TIMER_CMT bool "Renesas CMT timer driver" if COMPILE_TEST depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT help This enables build of a clocksource and clockevent driver for the Compare Match Timer (CMT) hardware available in 16/32/48-bit variants on a wide range of Mobile and Automotive SoCs from Renesas. config SH_TIMER_MTU2 bool "Renesas MTU2 timer driver" if COMPILE_TEST depends on HAS_IOMEM default SYS_SUPPORTS_SH_MTU2 help This enables build of a clockevent driver for the Multi-Function Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas. This hardware comes with 16 bit-timer registers. config RENESAS_OSTM bool "Renesas OSTM timer driver" if COMPILE_TEST select CLKSRC_MMIO help Enables the support for the Renesas OSTM. config SH_TIMER_TMU bool "Renesas TMU timer driver" if COMPILE_TEST depends on HAS_IOMEM default SYS_SUPPORTS_SH_TMU help This enables build of a clocksource and clockevent driver for the 32-bit Timer Unit (TMU) hardware available on a wide range SoCs from Renesas. config EM_TIMER_STI bool "Renesas STI timer driver" if COMPILE_TEST depends on HAS_IOMEM default SYS_SUPPORTS_EM_STI help This enables build of a clocksource and clockevent driver for the 48-bit System Timer (STI) hardware available on a SoCs such as EMEV2 from former NEC Electronics. config CLKSRC_QCOM bool "Qualcomm MSM timer" if COMPILE_TEST depends on ARM select TIMER_OF help This enables the clocksource and the per CPU clockevent driver for the Qualcomm SoCs. config CLKSRC_VERSATILE bool "ARM Versatile (Express) reference platforms clock source" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK && !ARCH_USES_GETTIMEOFFSET select TIMER_OF default y if MFD_VEXPRESS_SYSREG help This option enables clock source based on free running counter available in the "System Registers" block of ARM Versatile, RealView and Versatile Express reference platforms. config CLKSRC_MIPS_GIC bool depends on MIPS_GIC select TIMER_OF config CLKSRC_TANGO_XTAL bool "Clocksource for Tango SoC" if COMPILE_TEST depends on ARM select TIMER_OF select CLKSRC_MMIO help This enables the clocksource for Tango SoC config CLKSRC_PXA bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST depends on HAS_IOMEM select CLKSRC_MMIO help This enables OST0 support available on PXA and SA-11x0 platforms. config H8300_TMR8 bool "Clockevent timer for the H8300 platform" if COMPILE_TEST depends on HAS_IOMEM help This enables the 8 bits timer for the H8300 platform. config H8300_TMR16 bool "Clockevent timer for the H83069 platform" if COMPILE_TEST depends on HAS_IOMEM help This enables the 16 bits timer for the H8300 platform with the H83069 cpu. config H8300_TPU bool "Clocksource for the H8300 platform" if COMPILE_TEST depends on HAS_IOMEM help This enables the clocksource for the H8300 platform with the H8S2678 cpu. config CLKSRC_IMX_GPT bool "Clocksource using i.MX GPT" if COMPILE_TEST depends on (ARM \|\| ARM64) && CLKDEV_LOOKUP select CLKSRC_MMIO config CLKSRC_IMX_TPM bool "Clocksource using i.MX TPM" if COMPILE_TEST depends on ARM && CLKDEV_LOOKUP select CLKSRC_MMIO help Enable this option to use IMX Timer/PWM Module (TPM) timer as clocksource. config TIMER_IMX_SYS_CTR bool "i.MX system counter timer" if COMPILE_TEST select TIMER_OF help Enable this option to use i.MX system counter timer as a clockevent. config CLKSRC_ST_LPC bool "Low power clocksource found in the LPC" if COMPILE_TEST select TIMER_OF if OF depends on HAS_IOMEM select CLKSRC_MMIO help Enable this option to use the Low Power controller timer as clocksource. config ATCPIT100_TIMER bool "ATCPIT100 timer driver" depends on NDS32 \|\| COMPILE_TEST depends on HAS_IOMEM select TIMER_OF default NDS32 help This option enables support for the Andestech ATCPIT100 timers. config RISCV_TIMER bool "Timer for the RISC-V platform" depends on GENERIC_SCHED_CLOCK && RISCV default y select TIMER_PROBE select TIMER_OF help This enables the per-hart timer built into all RISC-V systems, which is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems. config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY select TIMER_OF help Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP system. csky,mptimer is not only used in SMP system, it also could be used single core system. It's not a mmio reg and it use mtcr/mfcr instruction. config GX6605S_TIMER bool "Gx6605s SOC system timer driver" if COMPILE_TEST depends on CSKY select CLKSRC_MMIO select TIMER_OF help This option enables support for gx6605s SOC's timer. config MILBEAUT_TIMER bool "Milbeaut timer driver" if COMPILE_TEST depends on OF depends on ARM select TIMER_OF select CLKSRC_MMIO help Enables the support for Milbeaut timer driver. config INGENIC_TIMER bool "Clocksource/timer using the TCU in Ingenic JZ SoCs" default MACH_INGENIC depends on MIPS \|\| COMPILE_TEST depends on COMMON_CLK select MFD_SYSCON select TIMER_OF select IRQ_DOMAIN help Support for the timer/counter unit of the Ingenic JZ SoCs. endmenu ��Makefile��0000644��00000010052�14722071066�0006207 0��ustar�00��# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_TIMER_OF) += timer-of.o obj-$(CONFIG_TIMER_PROBE) += timer-probe.o obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o obj-$(CONFIG_RENESAS_OSTM) += renesas-ostm.o obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o obj-$(CONFIG_EM_TIMER_STI) += em_sti.o obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o obj-$(CONFIG_IXP4XX_TIMER) += timer-ixp4xx.o obj-$(CONFIG_ROCKCHIP_TIMER) += timer-rockchip.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o obj-$(CONFIG_ARMADA_370_XP_TIMER) += timer-armada-370-xp.o obj-$(CONFIG_ORION_TIMER) += timer-orion.o obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o obj-$(CONFIG_MXS_TIMER) += mxs_timer.o obj-$(CONFIG_CLKSRC_PXA) += timer-pxa.o obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += timer-cadence-ttc.o obj-$(CONFIG_CLKSRC_EFM32) += timer-efm32.o obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o obj-$(CONFIG_CLKSRC_LPC32XX) += timer-lpc32xx.o obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o obj-$(CONFIG_RDA_TIMER) += timer-rda.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += timer-versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += timer-tango-xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o obj-$(CONFIG_TIMER_IMX_SYS_CTR) += timer-imx-sysctr.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o ��

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